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Integrated Circuit Systems, Inc.
ICS93V850
Preliminary Product Preview
DDR Phase Lock Loop Clock Driver
Recommended Application: DDR Clock Driver Product Description/Features: * Low skew, low jitter PLL clock driver * I2C for functional and output control * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * With bypass mode mux * Operating frequency 60 to 140 MHz Switching Characteristics: * PEAK - PEAK jitter (66MHz): <120ps * PEAK - PEAK jitter (>100MHz): <75ps * CYCLE - CYCLE jitter (66MHz):<120ps * CYCLE - CYCLE jitter (>100MHz):<65ps * OUTPUT - OUTPUT skew: <100ps * Slew Rate: 1V/ns - 2V/ns
GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT CLK_INC 2 VDDI C AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD SDATA FB_INC FB_INT VDD FB_OUTT FB_OUTC GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND
48-Pin TSSOP
Block Diagram
FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1
Functionality
INPUTS GND GND L H H L H L <20 MHz L H L H Hi-Z H L H L Hi-Z OUTPUTS L H L H Hi-Z H L H L Hi-Z AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC PLL State Bypassed/Off Bypassed/Off On On Off
SCLK SDATA
Control Logic
CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
2.5V L (nom) 2.5V H (nom) 2.5V <20 MHz (nom)
FB_INT FB_INC CLK_INC CLK_INT
CLKT5 CLKC5
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
AVDD
0423H--07/03/03 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS93V850
ICS93V850
Preliminary Product Preview
Pin Descriptions
PIN NUMBER PIN NAME TYPE PWR OUT OUT PWR IN IN IN PWR PWR PWR OUT Ground "Complementar y" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs. Power supply 2.5V Clock input of I2C input, 5V tolerant input "True" reference clock input "Complementar y" reference clock input 3.3V power for I2C Analog power supply, 2.5V A n a l o g gr o u n d . "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error. Data input for I2C serial input, 5V tolerant input DESCRIPTION 1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 4, 11, 21, 28, 34, 38, 45, 12 13 14 15 16 17 32 VDD SCLK CLK_INT CLK_INC V D D I 2C AVDD AGND FB_OUTC
33 35 36 37
FB_OUTT FB_INT FB_INC SDATA
OUT IN IN IN
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ICS93V850
Preliminary Product Preview
Byte 0: Output Control (1= enable, 0 = disable)
Byte 1: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 3, 2 5, 6 10, 9 20, 19 22, 23 46, 47 44, 43 39, 40
PWD 1 1 1 1 1 1 1 1
DESCRIPTION CLKT0, CLKC0 CLKT1, CLKC1 CLKT2, CLKC2 CLKT3, CLKC3 CLKT4, CLKC4 CLKT5, CLKC5 CLKT6, CLKC6 CLKT7, CLKC7
BIT PIN# PWD Bit 7 29, 30 1 Bit 6 27, 26 1 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 * Note: Do not change
Byte 3: Reserved (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
DESCRIPTION CLKT8, CLKC8 CLKT9, CLKC9 Reserved Reserved* Reserved* Reserved Reserved Reserved this bit value.
Byte 2: Reserved (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 4: Reserved (1= enable, 0 = disable)
Byte 5: Reserved (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Don't write into this register, writing into this register can cause malfunction
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ICS93V850
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . -0.5V to 3.6V (VDDI) . . . . . . . . . . . . . . . . . . . Logic Inputs: VI (except SCLK and SDATA) . . . . . . VI (SCLK and SDATA) . . . . . . . . . Logic Outputs: VO (except SDATA) . . . . . . . . . . . . . VO (SDATA) . . . . . . . . . . . . . . . . -0.5V to 4.6V -0.5 V to VDD +0.5 V -0.5 V to VDDI2C +0.5 V -0.5 V to VDD +0.5 V -0.5 V to VDDI2C +0.5 V
Input clamp current: IIK (VI < 0 or VI > VDD) . . . . +/- 50mA Output clamp current: IOK (VO < 0 or VO > VDD) +/- 50mA Continuous output current: IO (VO = 0 to VDD) . . +/- 50mA Package thermal impedance, theta JA: DGG package +89C/W Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output Low Current High Impedance Output Current Input Clamp Voltage High-level output voltage SYMBOL IIH IIL IDD2.5 IDDPD IOH IOL IOZ VIK VOH CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf CL = 0pf VDD = 2.3V, VOUT = 1V VDD = 2.3V, VOUT = 1.2V VDD=2.7V, Vout=VDD or GND Iin = -18mA VDD = min to max, IOH = -1 mA VDD = 2.3V, IOH = -12 mA VDD = min to max IOL=1 mA VDD = 2.3V IOH=12 mA VI = GND or VDD VOUT = GND or VDD MIN TYP MAX UNITS A A mA mA mA mA 10 mA V V V 0.1 0.6 V pF pF
100 -18 26
Low-level output voltage Input Capacitance1 Output Capacitance1
1
VOL CIN COUT
3
Guaranteed by design, not 100% tested in production.
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ICS93V850
Preliminary Product Preview
Recommended Operating Condition
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Analog/core supply voltage SYMBOL VDD, AVDD VDDI2C VIL VIH VID VIC VOC DC - CLK_INT, FB_INT AC - CLK_INT, FB_INT CONDITIONS MIN 2.3 2.3 -0.3 0.4 0.36 0.5 0.45x(VIH-VIL) TYP 2.5 MAX 2.7 3.6 VDD-0.4 VDD+0.3 VDDQ +0.6 VDDQ +0.6 0.55x(VIH-VIL) UNITS V V V V V V V V
Input voltage level Input differential-pair voltage swing1 Input differential-pair crossing voltage Output differential-pair crossing voltage
1 Differential inputs signal voltages specifies the differential voltage [VTR - VCP] required for switching, where VT is the true input level and VCP is the complementary input level.
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Operating clock frequency Input clock duty cycle CLK stabilization freqop dtin TSTAB from VDD = 3.3V to 1% target freq. 66 40 170 60 100 UNITS MHz % s
Switching Characteristics
PARAMETER Jitter; Absoulte Jitter Cycle to Cycle Jitter1 Phase error Output to Output Skew Pulse skew Half Period Jitter Typ: Propagation Delay Time Slew Rate SYMBOL Tjabs Tcyc -Tcyc t(phase error) Tskew Tskewp Tjitter Hp 66/100/133/166MHz Bypass Mode CLK to any output Load = 120/14pF CONDITION 66MHz 100/125/133/167MHz 66MHz 100/125/133/167MHz MIN TYP MAX 120 75 110 65 150 100 100 75 4 1 1.8 2 UNITS ps ps ps ps ps ps ps ps ns V/ns
-150
-75
t SLEW
Notes: 1. Refers to transition on noninverting output. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up.
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ICS93V850
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS93V850
Preliminary Product Preview
Recommended Layout for the ICS93V850
General Layout Precautions: Use copper flooded ground on the top signal layer under the clock buffer The area under U1 on the right is an example. Flood over the ground vias. 1) Use power vias for power and ground. Vias 20 mil or larger in diameter have lower high frequency impedance. Vias for signals may be minimum drill size. 2) Make all power and ground traces are as wide as the via pad for lower inductance. 3) VAA for pin 16 has a low pass RC filter to decouple the digital and analog supplies. The 4.7uF capacitors may be replaced with a single low ESR device with the same total capacitance. VAA is routed on a outside signal layer. Do not cut a power or ground plane and route in it. 4) Notice that ground vias are never shared. 5) When ever possible, VCC (net V2P5 in the schematic) pins have a decoupling capacitor. Power is always routed from the plane connection via to the capacitor pad to the VCC pin on the clock buffer. Moats or plane cuts are not used to isolate power. 6) Differential mode clock output traces are routed: a. With a ground trace between the pairs. Trace is grounded on both ends. b. Without a ground trace, clock pairs are routed with a separation of at least 5 times the thickness of the dielectric. If the dielectric thickness is 4.5 mil, the trace separation is at least 18 mils. 7) Terminate differential CLK_IN and FB_IN traces after routing to buffer pads. Component Values: Ref Desg. Value
C1,C4,C5, C7,C11,C12 C2,C3,C8, C9 C10 C6 R9,R12 R9 U1 .01uF 4.7uF .22uF 2200pF 120 4.7
Description
CERAMIC MLC CERAMIC MLC CERAMIC MLC CERAMIC MLC
Package
0603 1206 0603 0603 0603 0603 TSSOP48
ICS93701AG
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ICS93V850
Preliminary Product Preview
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48 D mm. MIN MAX 12.40 12.60 D (inch) MIN .488 MAX .496
-Ce
b SEATING PLANE
aaa C
6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil)
Ref erence Doc.: JEDEC Publicat ion 95, M O-153 10-0039
Ordering Information
ICS93V850yGT
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0423H--07/03/03
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